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Logs: freenode/#haskell

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2021-05-11 20:13:55 → jchia[m] joins (jchiamatri@gateway/shell/matrix.org/x-scatarnmpyydrxbt)
2021-05-11 20:13:55 → dominicusin[m] joins (dominicusi@gateway/shell/matrix.org/x-oatljpwlthdxnsxj)
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2021-05-11 20:13:57 × sphalerite quits (~sphalerit@NixOS/user/lheckemann) (Max SendQ exceeded)
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2021-05-11 20:16:28 × madjestic[m] quits (madjesticm@gateway/shell/matrix.org/x-bliesrnvyjhhztuj) (Ping timeout: 246 seconds)
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2021-05-11 20:16:59 × dominicusin[m] quits (dominicusi@gateway/shell/matrix.org/x-oatljpwlthdxnsxj) (Ping timeout: 276 seconds)
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2021-05-11 20:18:17 × jchia[m] quits (jchiamatri@gateway/shell/matrix.org/x-scatarnmpyydrxbt) (Ping timeout: 276 seconds)
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2021-05-11 20:18:22 × LKoen quits (~LKoen@156.168.9.109.rev.sfr.net) (Quit: “It’s only logical. First you learn to talk, then you learn to think. Too bad it’s not the other way round.”)
2021-05-11 20:18:33 <m_shiraeeshi> shapr: "Even then, all these cores still pretend to be one fast CPU! They have the same view of main memory! More cores means more overhead synchronizing the shared view of memory."
2021-05-11 20:18:43 → pavonia joins (~user@unaffiliated/siracusa)
2021-05-11 20:18:59 <m_shiraeeshi> what memory is it talking about?
2021-05-11 20:18:59 × Hanma[m] quits (hanmamatri@gateway/shell/matrix.org/x-cdkqqwjlurvjchsb) (Ping timeout: 248 seconds)
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2021-05-11 20:21:10 <m_shiraeeshi> so the idea is to have a lot of small cores, each core having its own memory?
2021-05-11 20:21:20 × hyiltiz quits (~quassel@unaffiliated/hyiltiz) (Ping timeout: 252 seconds)
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2021-05-11 20:22:36 → Feuermagier joins (~Feuermagi@213.178.26.41)
2021-05-11 20:23:20 <shapr> m_shiraeeshi: that sounds good to me, but that has its own problems
2021-05-11 20:23:42 <shapr> m_shiraeeshi: another solution is to magically decrease the cycle count to main memory, and remove the caches
2021-05-11 20:24:00 <m_shiraeeshi> main memory is RAM?
2021-05-11 20:24:06 shapr sprinkles unicorn dust
2021-05-11 20:24:09 → Tario joins (~Tario@201.192.165.173)
2021-05-11 20:24:23 → tromp joins (~tromp@dhcp-077-249-230-040.chello.nl)
2021-05-11 20:25:13 <shapr> m_shiraeeshi: at the momemt, yes... the FPGA designs has on-die RAM that's much faster https://www-users.york.ac.uk/~mt540/graceful-ws/slides/Stewart.pdf
2021-05-11 20:25:34 → jamm_ joins (~jamm@unaffiliated/jamm)
2021-05-11 20:26:57 <m_shiraeeshi> how about adding external "graph reduction card" like we add external graphics cards?
2021-05-11 20:27:31 <Rembane> shapr: I'm gonna be silly here, because tired. Does this parallel graph reduction idea mean that you implement Erlang on hardware?
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